This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-080410, filed Mar. 22, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a booster circuit having a plurality of booster units (booster cells) whose output terminals are respectively connected to input terminals of the next-stage booster units, for raising voltage by sequentially transferring charges from the input terminals of the booster units to the output terminals thereof in response to clock signals of different phases and more particularly to the technique for resetting the gate nodes of transistors of the booster units in which charges are left behind.
FIG. 1 is a circuit diagram showing an example of the construction of a conventional booster circuit. The booster circuit is described in IEEE Journal of Solid-State Circuits. Vol. 27, No. 11, November 1992, pp. 1540 to 1546, A. Umezawa et al. xe2x80x9cA 5-V-Only Operation 0.6-xcexcm Flash EEPROM with Row Decoder Scheme in Triple Well Structurexe2x80x9d.
The booster circuit is constructed by booster units (booster cells) 11a, 11b, booster unit 12 and output circuit section 13. Each of the booster units 11a, 11b, 12 is constructed by two MOS transistors (MOSFETs) and two capacitors and the output terminals thereof are cascade-connected to the input terminals of the next-stage booster units.
That is, the booster unit 11a includes N-channel MOS transistors QN1, QN2 and capacitors C1, C2. One-side ends of the current paths of the MOS transistors QN1, QN2 are connected to a power supply terminal 14 to which a power supply voltage VCC is applied. The other end of the current path of the MOS transistor QN2 is connected to the gate of the MOS transistor QN1 and the gate thereof is connected to the other end-of the current path of the MOS transistor QN1. One electrode of the capacitor C1 is connected to the other end of the current path of the MOS transistor QN1 and the other electrode of the capacitor C1 is supplied with a clock signal phi1. Further, one electrode of the capacitor C2 is connected to the gate of the MOS transistor QN1 and the other electrode of the capacitor C2 is supplied with a clock signal phi3.
Likewise, the booster unit 11b includes N-channel MOS transistors QN3, QN4 and capacitors C3, C4. One-side ends of the current paths of the MOS transistors QN3, QN4 are connected to the other end of the current path of the MOS transistor QN1. The other end of the current path of the MOS transistor QN4 is connected to the gate of the MOS transistor QN3 and the gate thereof is connected to the other end of the current path of the MOS transistor QN3. One electrode of the capacitor C3 is connected to the other end of the current path of the MOS transistor QN3 and the other electrode of the capacitor C3 is supplied with a clock signal phi2. Further, one electrode of the capacitor C4 is connected to the gate of the MOS transistor QN3 and the other electrode of the capacitor C4 is supplied with a clock signal phi4.
The booster unit 12 includes N-channel MOS transistors QN5, QN6 and capacitors C5, C6. One-side ends of the current paths of the MOS transistors QN5, QN6 are connected to the other end of the current path of the MOS transistor QN3. The other end of the current path of the MOS transistor QN6 is connected to the gate of the MOS transistor QN5 and the gate thereof is connected to the other end of the current path of the MOS transistor QN5. One electrode of the capacitor C5 is connected to the other end of the current path of the MOS transistor QN5 and the other electrode of the capacitor C5 is supplied with the clock signal phi1. Further, one electrode of the capacitor C6 is connected to the gate of the MOS transistor QN5 and the other electrode of the capacitor C6 is supplied with a clock signal phi3.
The output circuit section 13 is constructed by an N-channel MOS transistor QN7. One end of the current path of the MOS transistor QN7 is connected to the other end of the current path of the MOS transistor QN3 and the gate thereof is connected to the gate of the MOS transistor QN5. Further, a positive voltage VPP obtained by raising or boosting the power supply voltage VCC is output from the other end of the current path of the MOS transistor QN7.
With the above construction, when four-phase clock signals phi1, phi2, phi3, phi4 of different phases are input as shown in the timing chart of FIG. 2, the power supply voltage VCC is sequentially raised by the booster circuits 11a, 11b for each cycle of the clock signals and supplied to one end of the current path of the MOS transistor QN7. Further, the boosted or raised voltage is supplied to and further raised by the booster unit 12 to produce voltage VG which is in turn supplied to the gate of the MOS transistor QN7. Thus, the gate of the transfer MOS transistor QN7 of the final stage is overdriven by the booster unit 12 so as to prevent a lowering in the output voltage VPP by the threshold voltage of the MOS transistor QN7.
In the above four-phase booster circuit, if a high voltage is left behind on the gate node of each MOS transistor in an electrically floating state after termination of the boosting operation, the transfer MOS transistors QN1, QN3, QN7 maintain the ON state at the time of re-boosting operation and the boosting operation cannot be effected.
Therefore, as shown in FIG. 3, the construction in which resetting N-channel MOS transistors QN8 to QN13 are respectively connected between the connection nodes of the gates of the MOS transistors QN1 to QN6 and the capacitors C1 to C6 and a ground node (GND) is proposed. A reset signal RST is supplied to the gates of the MOS transistors QN8 to QN13.
With the above construction, the gate voltage VG of the transfer MOS transistor QN7 of the final stage is raised for each cycle of the clock signals phi1 to phi4 as shown in the timing chart of FIG. 4 and the output voltage VPP is raised to a desired voltage. Then, if the reset signal RST is set to the high level at the time of termination of the boosting operation to turn ON the MOS transistors QN8 to QN13 and ground and discharge the connection nodes of the gates of the MOS transistors QN1 to QN6 and the capacitors C1 to C6, then the transfer MOS transistors QN1, QN3, QN7 can be forcedly turned OFF, thereby making it possible to prevent occurrence of an erroneous operation in the re-boosting operation.
Further, as shown in FIG. 5, the construction in which a resetting N-channel MOS transistor QN21 is connected between the output node of the power supply voltage VPP and the ground node GND in the booster circuit shown in FIG. 3 is also known in the art. After termination of the boosting operation, the output node is grounded and reset by supplying the reset signal RST to the gate of the MOS transistor QN21.
Thus, in the case of the booster circuit for generating the positive voltage, each node can be relatively easily reset by using the N-channel MOS transistor having a source grounded and a gate supplied with the reset signal having an amplitude between the ground potential and the power supply voltage VCC.
Further, in the above document, a booster circuit for generating a negative voltage as shown in FIG. 6 is also disclosed. The circuit includes P-channel MOS transistors QP1 to QP7 instead of the N-channel MOS transistors QN1 to QN7 shown in FIG. 1. The input terminal of the first-stage booster unit 11a, that is, one end of the current path of each of the MOS transistors QP1, QP2 is connected to the ground node GND instead of the power supply terminal 14.
Likewise, a booster circuit for generating a negative boosted voltage as shown in FIG. 7 and including P-channel MOS transistors QP1 to QP13 instead of the N-channel MOS transistors QN1 to QN13 shown in FIG. 3 can be provided.
If the booster circuit for generating a negative boosted voltage as shown in FIG. 7 is constructed, it is necessary to supply a reset signal RSTxe2x80x2 with an amplitude between the ground potential and a preset negative boosted potential to the gates of the resetting P-channel MOS transistors QP8 to QP13. However, since the normal resetting signal RST is a signal whose amplitude lies between the ground potential and the power supply potential, the reset signal cannot be simply supplied to the gates of the P-channel MOS transistors QP8 to QP13. In order to create the rest signal RSTxe2x80x2, it is of course possible to provide a separate negative voltage generating circuit, but there occurs a problem that the circuit scale is made large and the control operation becomes complicated.
As described above, in the conventional booster circuit, it is required to create a reset signal having a large amplitude in order to reset the gate nodes of the transistors in which charges are left behind and a problem that the circuit scale is made large and the control operation becomes complicated occurs if a separate voltage generating circuit is used to create the reset signal.
Accordingly, an object of this invention is to provide a booster circuit capable of suppressing an increase in the circuit scale and simplifying the control operation even if it is so constructed as to reset the gate nodes of transistors in which charges are left behind.
Another object of this invention is to provide a semiconductor memory device having a booster circuit capable of suppressing an increase in the circuit scale and simplifying the control operation even if it is so constructed as to reset the gate nodes of transistors in which charges are left behind.
The above object of this invention can be attained by a booster circuit comprising a booster unit including an input terminal to which a power supply potential or ground potential is applied, an output terminal for outputting a positive or negative boosted potential, first and second clock input terminals to which first and second clock signals of different phases are input, and a reset signal input terminal to which a reset signal is input, the booster unit transferring charges from the input terminal to the output terminal in response to the first and second clock signals and turning ON resetting transistors in response to the reset signal after termination of the charge transfer to reset the gate nodes of transistors in which charges are left behind; wherein the potential of the reset signal for turning ON the resetting transistor is created based on the positive or negative boosted potential output from the output terminal.
Further, the above object of this invention can be attained by a booster circuit comprising a plurality of booster units which includes a first-stage booster unit having an input terminal applied with a power supply potential or ground potential and whose output terminals are respectively connected to the input terminals of the next stage booster units; and an output circuit section controlled by an output potential of the final-stage booster unit, for transferring an output potential of one of the booster units which lies in the preceding stage of the final-stage booster unit; wherein each of the booster units includes first and second clock input terminals to which first and second clock signals of different phases are input and a reset signal input terminal to which a reset signal is input, transfers charges from the input terminal to the output terminal in response to the first and second clock signals and turns ON resetting transistors in response to the reset signal after termination of the charge transfer to reset the gate nodes of transistors in which charges are left behind and the potential of the reset signal for turning ON the resetting transistor is created based on the positive or negative boosted potential output from the output circuit section.
Further, the above object of this invention can be attained by a booster circuit comprising a plurality of booster units including a first-stage booster unit having an input terminal applied with a power supply potential or ground potential and whose output terminals are respectively connected to the input terminals of the next stage booster units; an output circuit section controlled by an output potential of the final-stage booster unit, for transferring an output potential of one of the booster units which lies in the preceding stage of the final-stage booster unit; a reset pulse generator for using a positive or negative boosted potential output from the output circuit section as one of power supply potentials to create a reset signal having an amplitude between the positive or negative boosted potential and a ground potential and supplying the reset signal to each of the booster units to reset the gate nodes of transistors of the booster units in which charges are left behind; and a discharge circuit for discharging the node of the reset pulse generator to which the positive or negative boosted potential is applied after resetting the gate nodes of the transistors in which charges are left behind.
The above object of this invention can be attained by a semiconductor memory device comprising a booster circuit for raising voltage by sequentially transferring charges in response to clock signals having different phases; and a circuit operated based on an output voltage of the booster circuit; wherein the booster circuit includes a plurality of booster units including a first-stage booster unit having an input terminal applied with a power supply potential or ground potential and whose output terminals are respectively connected to the input terminals of the next stage booster units, and an output circuit section controlled by an output potential of the final-stage booster unit, for transferring an output potential of one of the booster units which lies in the preceding stage of the final-stage booster unit, each of the booster units has first and second clock input terminals to which first and second clock signals of different phases are input and a reset signal input terminal to which a reset signal is input, transfers charges from the input terminal to the output terminal in response to the first and second clock signals and turns ON resetting transistors in response to the reset signal after termination of the charge transfer to reset the gate nodes of transistors in which charges are left behind, and the potential of the reset signal for turning ON the resetting transistor is created based on the positive or negative boosted potential output from the output circuit section.
Further, the above object of this invention can be attained by a semiconductor memory device comprising a booster circuit for raising voltage by sequentially transferring charges in response to clock signals having different phases; and a circuit operated based on an output voltage of the booster circuit; wherein the booster circuit includes a plurality of booster units including a first-stage booster unit having an input terminal applied with a power supply potential or ground potential and whose output terminals are respectively connected to the input terminals of the next stage booster units, an output circuit section controlled by an output potential of the final-stage booster unit, for transferring an output potential of one of the booster units which lies in the preceding stage of the final-stage booster unit, a reset pulse generator for using a positive or negative boosted potential output from the output circuit section as one of power supply potentials to create a reset signal having an amplitude between the positive or negative boosted potential and a ground potential and supplying the reset signal to each of the booster units to reset the gate nodes of transistors of the booster units in which charges are left behind, and a discharge circuit for discharging the node of the reset pulse generator to which the positive or negative boosted potential is applied after resetting the gate nodes of the transistors in which charges are left behind.
With the above construction, since the output voltage of the booster section is used for creating the reset signal, the booster circuit can be constructed by use of a simple logic circuit, it becomes unnecessary to use a separate negative voltage generating circuit, and the gate nodes of the transistors of the booster unit in which charges are left behind can be reset by a relatively simple control operation. Therefore, a booster circuit capable of suppressing an increase in the circuit scale and making the control operation simple and a semiconductor memory device having the booster circuit can be provided.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.